Friday, 10 August 2018

What is VHDL


VHSIC Hardware Description Language (VHDL) is language for designing digital system, it is use to program FPGA,it is parallel programming language.The three type of modeling structural, data flow and behavioral. 


VHDL is developed 1983 for department of Defense (DoD) under the Very High Speed Integrated Circuit (VHSIC) program. 

Design unit: 

  1. Entity declaration 
  2.  Architecture 
  3. Configuration 
  4. Package declaration 
  5. Package body 


Entity declaration:

It defined the name of input and output and mode of hardware module.

Architecture:
Architecture describe the style, that is structural, data flow or behavioral.



Syntax:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;



entity first_design is

port(    );

end first_design;

architecture Behavioral of first_design is

begin

code Body/ statements;

end Behavioral;